FIG. 1 is a circuit diagram of a prior art differential amplifier or buffer carried by an integrated circuit chip and designed for linear analog amplification purposes. The circuit of FIG. 1 has wide range common-mode rejection properties. The wide range common-mode rejection properties, however, are accompanied by a substantial propagation delay for the common-mode signal differentially applied to terminals 10 and 12, which is coupled to single ended output terminal 14.
The prior art circuit of FIG. 1 includes driver circuit 16 and a pair of output circuits 18 and 20. Each of circuits 16, 18 and 20 includes at least one DC path having several three terminal semiconductor devices connected between positive DC power supply terminal 22 and ground terminal 24. In one typical amplifier, the semiconductor devices included in each of circuits 16, 18 and 20 are metal oxide semiconductor field effect transistors, each having a gate electrode for controlling current flow in a conducting path between source and drain electrodes. Each of output circuits 18 and 20 includes four transistors having stacked series connected source drain paths, such that circuit 18 includes field effect transistors 31-34, while circuit 20 includes field transistors 35-38. N-channel field effect transistors 31 and 35 are connected directly to ground terminal 24 while N-channel field effect transistors 32 and 36 are connected to ground terminal 24 through the source drain paths of transistors 31 and 35, respectively. P-channel field effect transistors 34 and 38 are connected directly to voltage V.sub.dd (typically at least 3 volts) at positive DC power supply terminal 22, and P-channel field effect transistors 33 and 37 are respectively connected to terminal 22 via the source drain paths of transistors 34 and 38.
Driver circuit 16 includes P-channel field effect transistor 41, having its source drain path connected to positive DC power supply voltage 22. Transistor 41 is a current source, such that the amount of DC current flowing in its source drain path is controlled by a DC bias voltage applied to the gate of transistor 41. The source drain path of transistor 41 drives the source drain paths of P-channel field effect transistors 42 and 43 in parallel. The source drain path of N-channel field effect transistor 44 (having its gate electrode driven by the same DC bias voltage that is applied to the gate of transistor 41) is a current source connected to ground (i.e., negative) DC power supply terminal 24. The source drain path of transistor 44 drives the source drain paths of N-channel field effect transistors 45 and 46 in parallel.
The gates (i.e., control electrodes) of transistors 42 and 45 are DC connected in parallel to input terminal 10 while the gates of transistors 43 and 46 are DC connected in parallel to input terminal 12. Thereby, as the voltage at terminal 10 increases relative to ground, the voltage between the source and drain of each of transistors 42 and 45 respectively decreases and increases and vice versa for decreasing voltages at terminal 10 relative to ground; similarly, in response to increases in the voltage at terminal 12 relative to ground, the voltages across the source drain paths of transistors 43 and 46 respectively decrease and increase.
The changes in voltages across the source drain paths of transistors 42-46 are DC coupled to paths 18 and 20. To this end, the drain of transistor 42 is connected to terminal 50, between the drain of transistor 31 and the source of transistor 32, while the drain of transistor 45 is connected to terminal 52, between the source of transistor 33 and the drain of transistor 34. As the voltage at terminal 10 increases relative to ground, (1) the gate source voltage of transistor 42 decreases, to decrease the voltage at the drain of transistor 42 relative to ground, whereby the voltage at terminal 50 decreases relative to ground; and (2) the gate source voltage of transistor 45 increases, to decrease the voltage at the drain of transistor 45 relative to ground, whereby the voltage at terminal 52 decreases relative to ground. The decrease in voltage at terminal 50 relative to ground increases the gate source voltage of transistor 50 to reduce the drain voltage of transistor 32, at terminal 58, relative to ground. The decrease in voltage at terminal 52 relative to ground decreases the gate source voltage of transistor 33 to increase the source drain voltage of transistor 33 and decrease the voltage at terminal 58 relative to ground.
Similarly, the output voltage at terminal 14, which is between the drains of transistors 36 and 37, goes down and up in response to the voltage at terminal 12 respectively increasing and decreasing. Common-mode rejection (i.e., cancellation at terminal 14 of like variations in amplitude and polarity of the otherwise differential or complementary variations at terminals 10 and 12) occurs because of variations of the bias voltage at terminal 58 in response to changes in the voltage at input terminal 10.
Since the voltages at terminals 10 and 12 vary in a complementary manner, except for common-mode variations on the voltages applied to these terminals, the voltages at terminals 50 and 52 decrease when the voltages at terminals 54 and 56 increase, and vice versa. Accordingly, in response to the complementary increasing and decreasing voltages at terminals 10 and 12 the bias voltage terminal 58 applies to the gates of transistors 35-38 goes down relative to ground, while the voltages at terminals 54 and 56, at the sources of transistors 36 and 37, go up relative to ground. As a result the gate source voltage of transistor 36 decreases to increase the voltage at the drain of transistor 36 relative to ground while the gate source voltage of transistor 37 increases to increase the voltage at the drain of transistor 37 relative to ground. Since the drains of transistors 36 and 37 are tied to output terminal 14, the voltage at terminal 14 increases relative to ground. Simultaneously, the gate source voltages of transistors 35 and 38 respectively decrease and increase, causing the drain voltages of transistors 35 and 38 to increase relative to ground. The increased voltages at the drains of transistors 35 and 38 relative to ground are coupled through the source drain paths of transistors 36 and 37 to also cause the voltage at output terminal 14 to increase.
The voltages across transistors 35-38 vary in response to the voltages at terminals 10 and 12 such that the voltage at terminal 14 is an inverted replica of the voltage at terminal 12 except for the common variations at terminals 10 and 12 which are canceled in the circuit. The voltages at terminals 10 and 12 are susceptible to changing together in response to external influences being supplied to leads connected between a differential analog source (not shown) and terminals 10 and 12. For example, if the voltages at terminals 10 and 12 both simultaneously go up by the same amount due to common mode variations, the bias voltage at terminal 58 decreases, while the voltages at terminals 54 and 56 decrease. Consequently, the voltages at the drains of transistors 35 and 38 increase relative to ground in response to the bias voltage change, while the voltages at these drains decrease in response to the decreased voltages at the drains of transistors 43 and 46. Whatever change occurs at the drains of transistors 43 and 46 is offset by changes in the voltages across the source drain paths of transistors 36 and 37 in response to the decreased bias voltage terminal 58 applies to the gates of transistors 36 and 37. Similarly, the drain of transistor 43 is connected to terminal 54 between the drain of transistor 35 and the source of transistor 36 while the drain of transistor 46 is connected to terminal 56, common to the source of transistor 37 and the drain of transistor 38. Thereby, the voltages at terminals 54 and 56 decrease relative to ground in response to increases of the voltage at terminal 12 relative to ground.
Bias voltage for all of the transistors of the circuit of FIG. 1 except for transistors 42, 43, 45 and 46 of driver 16, is derived from tap 58. Tap 58 is at an approximate mid-point between the voltages of power supply terminals 22 and 24, at a common terminal in circuit 18 for the drains of transistors 32 and 33. The bias voltage at tap 58 tends to follow changes in the voltage at terminal 10 because the source drain voltages of transistors 32 and 33 change in a complementary manner in response to the changes in voltage at terminal 10.
As mentioned before, the prior circuit of FIG. 1 is usually used for linear analog amplification. One of the reasons why the circuit of FIG. 1 has good common-mode rejection properties is because it does not have an external bias circuit. Instead, bias for all of the transistors, except transistors 42, 43, 45 and 46 which are driven directly by voltages at terminals 10 and 12, is derived from tap 58.
However, if the circuit of FIG. 1 is used as a buffer or amplifier of clock wave pulses on a very large scale integrated circuit chip (e.g., each side having a 2 centimeter length) there is a substantial pulse propagation delay and skew due to circuit variations resulting from semiconductor processing, changes in voltages at terminals 22 and 24 and temperature changes. Skew, which can occur as a function of time and space on the chip, is a phenomenon causing clock pulses to have different propagation delays so they arrive at different times to circuits at different regions on the chip. The voltages at terminals 22 and 24 are subject to variations because of relatively large impedances of leads connected between power supply terminals 22 and 24 and the various components at different locations on the chip directly connected to these terminals. In addition, the voltage at terminal 22 is subject to variations for the usual reasons associated with power supply variations.
One reason why the circuit of FIG. 1 is subject to substantial propagation delay and skew is because of a relatively low gate source voltage of its active load, particularly the active load including transistors 36 and 37. The gate source voltage of transistors 36 and 37 is equal to or less than the source drain voltages of these two transistors; the source drain voltage of transistors 36 and 37 is equal to or less than approximately 0.5 volts, for a typical DC power supply voltage of 3 volts between power supply terminals 22 and 24. The source drain voltages of transistors 36 and 37 are thus considerably smaller than the source drain voltages of transistors 35 and 38 which are directly connected to power supply terminals 24 and 22, respectively.
If terminals 10 and 12 were connected to a pulse source, such as active differential nodes of a clock source formed by a phase lock loop, transistors 32, 33, 36 and 37 would turn off early during a pulse transition time from one level to another. This is because the gate electrodes of transistors 32, 33, 36 and 37 are biased by the voltage at tap 58. The voltage at tap 58 is, in turn, dependent on the conducting states of transistors 42, 43, 45 and 46. Hence, as transistors 42 and 45 turn off and turn on, the conducting states of transistors 32 and 33 are changed and the current flowing to terminal 58 changes accordingly. As a result, there are relatively slow transitions in the voltage at tap 58 in response to changes in the levels of the voltages at terminals 10 and 12. These changes in the voltage at tap 58 result in slow changes at the gates of transistors 36 and 37 and slow changes in the current flowing through the source drain conducting paths of transistors 36 and 37. These factors cause a substantial propagation delay time of voltage transitions at output terminal 14 between the drains of transistors 36 and 37 relative to the transition times of the voltages at terminals 10 and 12.
Another disadvantage of the circuit of FIG. 1, if it were used in response to bi-level clock pulses at terminals 10 and 12, is that the "trip voltage" of the circuit has a tendency to vary. Desirably, the circuit of FIG. 1, if driven by bi-level clock pulses at terminals 10 and 12, changes state when the voltage at terminal 10 increases relative to the voltage at terminal 12 by a value that is one-half of the power supply voltage between terminals 22 and 24. However, because the circuit of FIG. 1 is subject to variations in the power supply voltages at both terminals 22 and 24, variations occur in the voltages at terminal 58, which controls the voltages at which transistors 35-38 switch between on and off states.
It is, accordingly, an object of the present invention to provide a new and improved common-mode differential buffer particularly adapted to respond to bi-level variations, e.g., as are in pulses of clock waves.
Another object of the present invention is to provide a new and improved differential buffer having substantial common-mode rejection, and a short propagation delay time between bi-level transitions at an input terminal of the buffer to the buffer output terminal.
Another object of the invention is to provide a new and improved integrated circuit differential buffer responsive to common-mode signals and having high common-mode rejection, wherein skew due to semiconductor processing, power supply voltage changes and temperature variations is minimized.
An additional object of the present invention is to provide a new and improved integrated circuit differential buffer having high common-mode rejection properties and a relatively constant trip voltage in response to bi-level inputs, despite variations in power supply voltages.
Another object of the present invention is to provide a new and improved integrated circuit differential buffer or amplifier having high common-mode rejection and a pair of output transistors which operate at relatively high speed because they have a relatively high gate-source voltage even though the circuit is self biased, i.e., does not include an external bias source for control electrodes of semiconductor devices in the circuit.
Another object of the present invention is to provide a new and improved integrated circuit low skew differential buffer with a wide range of common-mode noise rejection, wherein the buffer and integrated circuit are particularly adapted to operate with very low DC power supply voltages, such as 1.3 volts.